1. Field of the Invention
The present invention relates to a structure of semiconductor devices, and more particularly relates to a structure having an enhancement in high current drive capability and a diminishment in the area occupied by devices.
2. Description of the Prior Art
Integrated circuits (ICs) are gradually stepping toward highly dense targets in order to comply with developments and changes in time and technology. The trend is toward gradual diminishment in semiconductor device sizes and distances between devices. Therefore, even though the sizes of semiconductor devices are being reduced to a measuring unit that is as small as angstroms, it is still very important to maintain the best operating condition within the devices. In particular, it is necessary to require little effort in achieving high current drive capability under high voltage operations. Conventional structures of high voltage CMOS (HV-CMOS) devices have channels and drift regions in the horizontal direction, which result in a larger chip area occupation. Therefore, a better and more advanced device structure is needed urgently.
FIG. 1 shows a cross-sectional view of a structure of a conventional CMOS transistor. The structure comprises a p-type conductivity substrate 10, a N.sup.+ source electrode 11, a N.sup.+ drain electrode 12, a drift region 13, a field oxide (FOX) layer 14, a gate oxide layer 15, and a gate electrode 16.
In the structure of a conventional CMOS transistor described above, channel and drift regions are all in the horizontal direction and only source and drain electrodes are located inside the substrate. This type of structure makes channel and drift regions of the CMOS seems shorter in length. When the channel of the CMOS device is reduced in length, hot carrier effects would become more serious. And yet, there are many ways of solving hot carrier effects for short channel length CMOS devices. The simplest method would be to reduce the CMOS transistor's operating voltage. For example, given a 5V reduced to 3.3V or even 2.5V, such a reduction would reduce the channel's horizontal electric field and would result in an inability to form any hot carrier. Although the phenomena of "carrier multiples" can be greatly reduced, the device would not be able to be used for high voltage operations. If there is a desire to avoid reducing the operating voltage for CMOS transistors and also solving hot carrier effects for short channel length CMOS devices, then the channel length of CMOS devices needs to be increased. The structure in horizontal direction and an increase in the channel length would occupy a greater chip area, which is against the trend of gradual diminishment in the sizes of semiconductor devices.
Another method that is popular for use in solving hot carrier effects for short channel length CMOS devices is placing a N.sup.- type region with lower doping density at the place where the source/drain region draws near the channel. This kind of design has been called --"Lightly Doped Drain", or its initial LDD. The use of LDD is not a perfect solution. First of all, LDD makes CMOS fabrication more complicated. Next, due to lower doping density of LDD, the series resistance between source and drain would be higher, causing a reduction in the device's operating speed and an increment in power dissipation.
Furthermore, due to lower doping density under the gate oxide layer, the resistance also goes higher and results in a weaker current drive capability. The structure of source and drain region is symmetrical and both sides have low doping density. The overall current drive capability would be even weaker. And finally, this kind of transistor structure would easily form parasitic bipolar effects under high voltages.